1. Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form an interconnection between an overlying bit line and an underlying contact plug.
2. Description of the Prior Art
The objective of the semiconductor industry, to continually decrease the size of dynamic random access memory, (DRAM), or static random access memory, (SRAM), devices, used for advanced integrated circuits, (IC), is dependent on the ability of specific semiconductor disciplines, to improve processes and tools, that will enable device features of less than 0.25 um, to be realized. Advances in photolithographic exposure tools, have allowed short wavelengths, using KrF, (248 nm), or ArF, (193 nm), to be achieved, however to achieve features of 0.1 um, or less, specific semiconductor elements, such as conductive interconnect structures, and the fabrication processes needed to create these elements at reduced dimensions, are needed, in addition to the advances in photolithographic disciplines.
This invention will describe a novel process resulting in structural innovations that will allow sub-quarter micron features, to be achieved without taxing the photolithographic discipline, by increasing exposure resolution, or by demanding more sensitive photolithographic alignment and critical image control. One features of this invention is the use of merging three contact plug openings, created self-aligned to adjacent gate structures, via use of a single stripe type contact opening, therefore easing patterning difficulties encountered with conventional processes, in which individual openings are formed to individual plug structures. In addition this invention also features the use of a bit line structure, self-aligned to, and contacting the sidewall of, an underlying contact plug structure, in a non-active device region, thus easing the patterning procedure, used with conventional bit line contacts in which an opening to a plug structure is formed in an active device region. Prior art, such as Witek et al, in U.S. Pat. No. 5,393,681, as well as Woo et al, in U.S. Pat. No. 5,451,543, describe methods of forming sidewall contacts, however these prior arts do not describe the merged contact plug approach, or the sidewall contact of a bit line structure to a contact plug, in a non-active device region.